1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection in integrated circuit structures and, in particular, to silicon controlled rectifier (SCR) structures that utilize lightly doped diffusion (LDD) junction breakdown as a low voltage trigger circuit.
2. Discussion of the Prior Art
FIG. 1 shows circuitry 10 for electrostatic discharge protection (ESD) of an integrated circuit structure. As shown in FIG. 1, ESD protection circuitry 10 includes a resistor R connected between a signal pad 12 and the internal circuits to be protected. The signal pad 12 is further connected to an anode of a silicon controlled rectifier (SCR) structure 14. The cathode of the SCR structure 14 is connected to ground. A field plate diode (FPD) 16 is connected between the signal line 18 to the internal circuits and ground. The FPD 16 has a breakdown voltage of approximately 15 V.
When a high voltage, i.e., approximately 15 V or greater, is applied to signal pad 12, the FPD 16 is the first element of the ESD protection circuitry 10 to break down, going into bipolar snapback. When this occurs, the current flow through resistor R determines the voltage build-up at signal pad 12 to turn on SCR 14 to provide an additional current path to ground for protection of the internal circuits. As shown in FIG. 2, after the SCR 14 turns on, the power dissipation in the SCR 14 is reduced with the anode-cathode potential clamped at a lower voltage V.sub.h.
Although the FPD 16 responds to the 15 V level, in order to initiate the flow of current through the SCR structure 14, a trigger voltage of approximately 50 volts is required between its anode and its cathode. Because of the relatively small current flow through the resistor R, a very large resistor value is needed in order to obtain the required 50 V. A large resistor value is undesirable, however, because it results in consumption of large die area and increases RC delay, thus slowing down switching times on the signal line 18.
U.S. Pat. No. 5,225,702, issued Jul. 6, 1993, discloses a SCR structure, shown in FIG. 3, that is triggered by the n-well/p-well junction at approximately 50 V. In the FIG. 3 SCR structure 300, when the voltage at anode 302 is less than approximately 50 V relative to the voltage at cathode 304, the junction 306 between n-well 308 and p-type semiconductor region 310 is reverse biased such that very little current is conducted by the SCR structure 300. For current to be conducted, the voltage at the anode 302 must be at least approximately 50 V, relative to the voltage at cathode 304, in order to create avalanche production of carriers at the junction 306.
FIG. 4 shows an improved SCR structure 400 for use in ESD protection that is triggered by MOSFET snapback at approximately 15 V. SCR structure 400, also disclosed in the '702 patent, provides a lower trigger voltage of approximately 15 V because the electric field between heavily doped n+ region 402 and p-type semiconductor region 404 is higher than the electric field between lightly doped n-well 406 and p-type region 404. Thus, the avalanche production of carriers is created between n+ region 402 and p-type region 404 more easily than between n-well 406 and p-type region 404. Avalanche production of carriers between n+ region 402 and p-type region 404 provides a bias current to the base of the npn transistor defined by heavily doped n+ region 408 (emitter), p-type region 404 (base) and n-well 406 (collector), thereby turning on the npn transistor to initiate flow of current through SCR structure 400 from anode 410 to cathode 412.
Furthermore, the trigger voltage of the SCR structure 400 is reduced because a higher electric field is created across junction 414 between n-well 406 and p-type region 404 when the voltage at anode 410 is positive relative to the voltage at cathode 412. This is due to the fact that the voltage potential between anode 410 and cathode 412 drops across a relatively small distance as applied by polysilicon gate layer 416 across thin gate oxide 418 more proximate to the junction 414 between n-well 406 and p-type region 404.
However, the FIG. 4 approach still has the disadvantage of requiring large die area due to the need for resistor R and the field plate diode (FPD), with possible latent damage resulting from the high snapback voltage at the FPD. Furthermore, the FIG. 4 solution is not applicable to low-voltage integrated circuit technologies because of the thin gate oxide 418 utilized in these low voltage structures.
U.S. Pat. No. 5,276,350, issued Jan. 4, 1994, discloses a low reverse junction breakdown voltage zener diode structure, shown in FIG. 5, for ESD protection of integrated circuits. As shown in FIG. 5, the diode structure 500 includes a heavily doped N+ cathode region 502 and a heavily doped P+ anode region 504 formed in a N- or P- semiconductor substrate 506. A lightly doped diffusion (LDD) region 508 is formed between the cathode region 502 and the anode region 504. By using the LDD implant as part of the diode fabrication process, a zener diode with a breakdown voltage of approximately 6.6 V is created.